Journal of Engineering, Computers & Applied Sciences (JEC&AS) ISSN No: 2319-5606 Volume 2, No.2, February 2013 _________________________________________________________________________________

Test compression has become a de-facto technique in VLSI testing. Test data volume is a serious concern for the semiconductor testing because it not only prolongs the testing time of the integrated circuits (Ics), but also raises the tester memory depth requirements and excessive capture power at-speed testing has also become a serious concern. So it is important to co-optimize test power and compression ratio in atspeed testing. A LPHCl X-filling framework is proposed to reduce capture power of both LoC and LoS atspeed testing, which is applicable for different test compression schemes. The proposed technology has been validated by the experimental results on larger ITC’99 benchmark circuits.